In a flash memory device, a verification operation is required to confirm that charges are injected into memory cells suitably by means of programmed operation. If the verification operation fails, the programmed operation and verification operation may be repeated, until the result of verification operation shows success or meets specific conditions (for instance, repeated 100 verification failures).
During the erase operation, a verification operation is similarly conducted, so as to confirm that charges are suitably removed from the memory cells until Vth of the memory cells are −ve. Vth is the gate voltage require to turn on floating gate core cell. When pgm/erase the core cell, that voltage will be modified. The terms “−ve (negative)” and “Vth” mean that the core cell is turn on even gate voltage is 0V. The erase verification is conducted such that the bitline is precharge to a voltage level and erased cells discharge the bitline. A page buffer connected at the end of the bitline and verify discharged bitline. Page buffer output a signal of passing verification if all selected bitlines are discharged.
Once breakage of a bit line occurs in the memory cell due to defects or other failures in manufacturing process, the memory cell having broken bit line is replaced by a redundant memory cell. However, the verification procedure, originated from an instruction of erase verification ERV, with respect to the broken bitline is still verify, and is not stopped until timeout.